Semiconductor element having grooves which divide an electrode layer, and method of forming the grooves

ABSTRACT

A semiconductor element is disclosed including a construction with electrode-dividing grooves, in which a dark current is smaller than in existing examples. A method of forming such grooves is also disclosed. In an embodiment, grooves, which electrically divide an electrode layer formed on the surface of a substrate, are formed with a V-shaped cross-sectional shape, groove side walls in the electrode layer, constituting the grooves, being sloping surfaces. An embodiment of the method of forming the grooves includes using a dicing blade having a blade distal end portion which is sharpened into a V-shape to cut a semiconductor wafer in which multiple patterns of semiconductor elements including an electrode layer on the surface of a substrate are formed, forming the grooves having a V-shaped cross-sectional shape which divide the electrode layer in each semiconductor element.

PRIORITY STATEMENT

The present application hereby claims priority under 35 U.S.C. §119 toJapanese patent application number JP 2013-120970 filed Jun. 7, 2013,the entire contents of which are hereby incorporated herein byreference.

TECHNICAL FIELD

At least one embodiment of the technique disclosed herein generallyrelates to a technique for forming grooves in a semiconductor element bycutting, for example by dicing.

BACKGROUND

Currently, in various fields such as nuclear physics and radiotherapyuse is made of semiconductor elements for detecting radiation, formedfrom group II-VI semiconductors, typically CdTe-based compoundsemiconductors. In recent years it has been proposed to obtain imagesusing these semiconductor elements, and in order to achieve this it isdeemed necessary for an electrode layer formed on the surface of theelement to be divided electrically to form a pixelated semiconductorelement which has multiple pixels (picture elements). One technique forforming such a pixelated semiconductor element is disclosed in JapanesePatent Kokai 2004-128238.

Japanese Patent Kokai 2004-128238 discloses a method in which anelectrode layer on a substrate surface is cut mechanically by half-cutdicing or the like, the electrode being divided by means of the cutgrooves. More specifically, a semiconductor wafer is subjected tohalf-cutting by dicing using a dicing blade (dicing saw), formingdividing grooves having a rectangular cross section and a target widthof 50 to 200 μm, as shown in FIG. 2 of Japanese Patent Kokai2004-128238.

A dark current (leakage current) is a factor which determines theperformance of a semiconductor element for detecting radiation. Toelaborate, it is known that an element having a small dark current has ahigh performance, and it is thus essential to reduce the dark current inorder to improve the performance of future semiconductor elements. Onthe other hand, with a construction having dividing grooves formed usingthe abovementioned known mechanical cutting method it is difficult tosuppress the dark current to a level that can meet existing or futuredemands, and it is problematic for semiconductor elements havingsatisfactory performance to be manufactured with a good yield.

SUMMARY

At least one embodiment the present invention proposes a semiconductorelement having a grooved construction in which the dark current issmaller than in existing examples, and a method of forming such grooves.

A semiconductor element according to one mode of embodiment of thepresent invention, proposed in response to the problems, is providedwith an electrode layer formed on the surface of a substrate, andgrooves which electrically divide said electrode layer, characterized inthat groove side walls in the abovementioned electrode layer,constituting the abovementioned grooves, are sloping surfaces. In onemode of embodiment, the cross-sectional shape of such grooves can beV-shaped or U-shaped with corner portions of the opening thereof beingchamfered.

One mode of embodiment of a method of forming the grooves in theabovementioned semiconductor element according to the present inventionincludes using a dicing blade having a blade distal end portion which issharpened into a V-shape to cut a semiconductor wafer in which multiplepatterns of semiconductor elements comprising an electrode layer on thesurface of a substrate are formed, forming the grooves having a V-shapedcross-sectional shape which divide the electrode layer in eachsemiconductor element.

Another mode of embodiment of a method of forming the grooves accordingto the present invention includes using a first dicing blade having ablade distal end portion which is sharpened into a V-shape to cut asemiconductor wafer in which multiple patterns of semiconductor elementscomprising an electrode layer on the surface of a substrate are formed,and after this cutting has been performed, using a second dicing bladehaving a blade width that is narrower than a blade width of the firstdicing blade to increase the depth of said V-shaped grooves, forminggrooves the corner portions of the openings of which are chamfered andwhich divide the electrode layer in each of the semiconductor elements.

Yet another mode of embodiment of a method of forming the groovesaccording to the present invention includes using a first dicing bladeto cut a semiconductor wafer in which multiple patterns of semiconductorelements comprising an electrode layer on the surface of a substrate areformed, and after this cutting has been performed, using a second dicingblade, having a blade width that is wider than a blade width of thefirst dicing blade and having a blade distal end portion that issharpened into a V-shape, to cut corner portions of the openings of saidgrooves, forming grooves the corner portions of the openings of whichare chamfered and which divide the electrode layer in each of thesemiconductor elements.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-described properties, features and advantages of thisinvention, and also the way in which they are achieved, will beexplained more clearly and precisely in connection with the followingdescription of the example embodiments which will be explained ingreater detail in connection with the drawings, in which:

FIG. 1 is a drawing illustrating an example of a dicing method whereby asemiconductor wafer is cut to form grooves.

FIG. 2 is a drawing illustrating another example of a dicing methodwhereby a semiconductor wafer is cut to form grooves.

FIG. 3 is a drawing illustrating an embodiment of a dicing blade used toform grooves.

FIG. 4 is a schematic cross-sectional view of a semiconductor elementaccording to a first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a semiconductor elementaccording to a second embodiment of the present invention.

FIG. 6 is a schematic plan view of semiconductor elements, illustratingthe arrangement of grooves according to the dicing method in FIG. 1 andthe arrangement of grooves according to the dicing method in FIG. 2.

FIG. 7 is a graph comparing the dark currents in a semiconductor elementhaving rectangular grooves and a semiconductor element having V-shapedgrooves.

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully withreference to the accompanying drawings in which only some exampleembodiments are shown. Specific structural and functional detailsdisclosed herein are merely representative for purposes of describingexample embodiments. The present invention, however, may be embodied inmany alternate forms and should not be construed as limited to only theexample embodiments set forth herein.

Accordingly, while example embodiments of the invention are capable ofvarious modifications and alternative forms, embodiments thereof areshown by way of example in the drawings and will herein be described indetail. It should be understood, however, that there is no intent tolimit example embodiments of the present invention to the particularforms disclosed. On the contrary, example embodiments are to cover allmodifications, equivalents, and alternatives falling within the scope ofthe invention. Like numbers refer to like elements throughout thedescription of the figures.

Before discussing example embodiments in more detail, it is noted thatsome example embodiments are described as processes or methods depictedas flowcharts. Although the flowcharts describe the operations assequential processes, many of the operations may be performed inparallel, concurrently or simultaneously. In addition, the order ofoperations may be re-arranged. The processes may be terminated whentheir operations are completed, but may also have additional steps notincluded in the figure. The processes may correspond to methods,functions, procedures, subroutines, subprograms, etc.

Methods discussed below, some of which are illustrated by the flowcharts, may be implemented by hardware, software, firmware, middleware,microcode, hardware description languages, or any combination thereof.When implemented in software, firmware, middleware or microcode, theprogram code or code segments to perform the necessary tasks will bestored in a machine or computer readable medium such as a storage mediumor non-transitory computer readable medium. A processor(s) will performthe necessary tasks.

Specific structural and functional details disclosed herein are merelyrepresentative for purposes of describing example embodiments of thepresent invention. This invention may, however, be embodied in manyalternate forms and should not be construed as limited to only theembodiments set forth herein.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments of thepresent invention. As used herein, the term “and/or,” includes any andall combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being“connected,” or “coupled,” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected,” or “directly coupled,” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between,” versus “directly between,” “adjacent,” versus“directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments of the invention. As used herein, the singular forms “a,”“an,” and “the,” are intended to include the plural forms as well,unless the context clearly indicates otherwise. As used herein, theterms “and/or” and “at least one of” include any and all combinations ofone or more of the associated listed items. It will be furtherunderstood that the terms “comprises,” “comprising,” “includes,” and/or“including,” when used herein, specify the presence of stated features,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, e.g., those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper”, and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, term such as “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein are interpreted accordingly.

Although the terms first, second, etc. may be used herein to describevarious elements, components, regions, layers and/or sections, it shouldbe understood that these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are used onlyto distinguish one element, component, region, layer, or section fromanother region, layer, or section. Thus, a first element, component,region, layer, or section discussed below could be termed a secondelement, component, region, layer, or section without departing from theteachings of the present invention.

Several embodiments of the present invention will now be described withreference to the drawings. In the embodiments described hereinbelow, asemiconductor element for detecting radiation, formed using a CdTesemiconductor from among the group II-VI semiconductors, is shown by wayof example. This semiconductor element is a pixelated semiconductordetection element having an electrode layer on the surface (one or bothof the main obverse surface and the reverse surface) of a CdTecrystalline substrate, the electrode layer being electrically divided bymeans of grooves which penetrate through the electrode layer to theinterior of the substrate, forming multiple pixel electrodes.

FIG. 1 and FIG. 2 illustrate dicing methods in which grooves are formedby cutting a CdTe semiconductor wafer 1 in which are formed patterns ofsemiconductor elements having an electrode layer (before cutting) on thesurface of a CdTe crystalline substrate. When dicing is to be performed,full-cut dicing lines 2 indicated by solid lines and half-cut dicinglines 3 indicated by dotted lines are defined taking an orientation flatla on the semiconductor wafer 1 as a reference. The full-cut dicinglines 2 are lines for cutting and separating the elements, establishedbetween each semiconductor element 10. On the other hand, the half-cutdicing lines 3 are groove-forming lines for dividing the electrode layeron the substrate surface in each respective semiconductor element 10. Bycarrying out dicing along the half-cut dicing lines 3, in the case inFIG. 1, multiple pixel electrodes, pixelated in the shape of scanninglines, are formed in each semiconductor element 10, and in the case inFIG. 2, multiple pixel electrodes, pixelated in the shape of dots, areformed in each semiconductor element 10.

An embodiment of a dicing blade used to effect half-cut dicing alonglines 3 such as those illustrated in FIG. 1 and FIG. 2, is illustratedin FIG. 3. FIG. 3A and FIG. 3B illustrate schematically a blade assembly20 which is mounted on a dicing device, which is not shown in thedrawings, and FIG. 3C and FIG. 3D illustrate in detail a dicing blade 21which is fixed to the blade assembly 20.

FIG. 3A is a plan view of the blade assembly 20, and FIG. 3B is across-sectional view as seen through the section line X-X in FIG. 3A. Inthe drawings, the dicing blade 21 is fixed to a peripheral edge portionof a disk-shaped blade attachment 22 by clamping or the like, the bladeattachment 22, to the circumferential edge portion of which the dicingblade 21 is fixed, being mounted by means of a shaft support hole 22 aat its center on a rotating shaft of the dicing device which is notshown in the drawings.

The details of the dicing blade 21 are as illustrated in FIG. 3C andFIG. 3D. FIG. 3C is a plan view of the dicing blade 21, and FIG. 3D isan enlarged cross-sectional view of the dicing blade 21 as seen throughthe section line Y-Y in FIG. 3C. The dicing blade 21 is ring-shaped, aninner circumferential edge portion 21 a thereof being fixed to thecircumferential edge portion of the blade attachment 22. The outercircumferential edge portion of the dicing blade 21, in other words theblade distal end portion 21 b, is sharpened into a V-shape, serving as acutting edge for dicing.

FIG. 4 is a cross-sectional view illustrating multiple grooves formed byeffecting the dicing shown in FIG. 1 or FIG. 2 using this dicing blade21. The grooves 30 illustrated in FIG. 4 are formed by using the dicingblade 21, the blade distal end portion 21 b of which has been sharpenedinto a V-shape as illustrated in FIG. 3, to cut the semiconductor wafer1, in which multiple patterns of semiconductor elements 10 have beenformed, along the dicing lines 3 illustrated in FIG. 1 or FIG. 2 usinghalf-cut dicing. Said grooves 30 have a V-shaped cross-sectional shapewhich divides the electrode layer in each semiconductor element 10. Theangle of the distal end cutting edge of the dicing blade 21 which formsthe V-shapes is at least equal to 40° and at most equal to 120°.

Each individual semiconductor element 10 has on the outer surfaces of aCdTe crystalline substrate 11, in the case shown in FIG. 4 on both amain obverse surface 11 a and a reverse surface 11 b, a first electrodelayer 12 and a second electrode layer 13. Of these, the first electrodelayer 12 formed on the main obverse surface 11 a is electrically dividedby means of grooves 30 having a V-shaped cross-sectional shape formed bythe abovementioned cutting. The cross-sectional shape of each groove 30is formed in a V-shape, and therefore groove side walls 12 a in thefirst electrode layer 12, constituting the grooves 30, are slopingsurfaces (inclined surfaces that are not perpendicular to the mainobverse surface 11 a). A blade width d (see FIG. 3D) of the dicing blade21 for forming the grooves 30 is such that d w relative to an openingwidth w (see FIG. 4) of the grooves 30.

FIG. 5 is a cross-sectional view illustrating multiple grooves formed byeffecting the dicing shown in FIG. 1 or FIG. 2 using the dicing blade 21and a separate dicing blade having a rectangular blade distal endportion such as that in Japanese Patent Kokai 2004-128238, the entirecontents of which are hereby incorporated herein by reference. Thegrooves 40 illustrated in FIG. 5 divide the electrode layer in eachsemiconductor element 10, corner portions of the openings thereof beingchamfered (12 a). The semiconductor element 10 has the same constructionas in the case in FIG. 4, except for the grooves 40, the first electrodelayer 12 formed on the main obverse surface 11 a being electricallydivided by way of the grooves 40.

The grooves 40 illustrated in FIG. 5 are formed by a two-stage cuttingprocess as described hereinbelow.

Firstly, using a first dicing blade 21, the blade distal end portion 21b of which has been sharpened into a V-shape as illustrated in FIG. 3Cand FIG. 3D, the semiconductor wafer 1, in which multiple patterns ofsemiconductor elements 10 have been formed, is cut along the dicinglines 3 illustrated in FIG. 1 or FIG. 2 using half-cut dicing.

Next, using a second dicing blade (which is omitted from the drawings)the blade distal end portion of which is rectangular and which has ablade width d′ that is narrower than the width of the openings of theV-shaped grooves formed by cutting using the first dicing blade 21,half-cut dicing is effected along the dicing lines 3. By this means theV-shaped grooves (the substrate 11 exposed within the grooves) formed bythe first dicing blade 21 are made deeper. In this process, the bladewidth d′ that is narrower than the width of the openings of the V-shapedgrooves can be achieved by arranging that, compared with the blade widthd illustrated in FIG. 3D, [the blade width d′ of the second dicingblade]<[the blade width d of the first dicing blade 21]. The blade widthd of the first dicing blade 21 is such that d≧w (the width of theopenings of the grooves 40).

Further, the two-stage cutting process forming the grooves 40 can bemodified as follows.

Firstly, using as a first dicing blade a dicing blade (which is omittedfrom the drawings) the blade distal end portion of which is rectangular,the semiconductor wafer 1, in which multiple patterns of semiconductorelements 10 have been formed, is cut along the dicing lines 3illustrated in FIG. 1 or FIG. 2 using half-cut dicing.

Next, using a second dicing blade 21, a blade distal end portion 21 b ofwhich is sharpened into a V-shape and which has a blade width that iswider than the width of the openings of the U-shaped grooves formed bycutting using the first dicing blade, half-cut dicing is effected alongthe dicing lines 3. By this means the corner portions of the openings ofthe U-shaped grooves formed by the first dicing blade (in other wordsthe corner portions of the electrode layer 12) are cut. In this process,if the blade width of the first dicing blade is d′, a blade width thatis wider than the width of the openings of the U-shaped grooves can beachieved by arranging that, compared with the blade width d illustratedin FIG. 3D, [the blade width d′ of the first dicing blade]<[the bladewidth d of the second dicing blade 21]. The blade width d of the seconddicing blade 21 is such that d≧w (the width of the openings of thegrooves 40).

According to these groove-forming processes, a cutting process isincluded that uses a wide dicing blade 21 the blade distal end portion21 b of which is sharpened into a V-shape, and therefore the walls ofthe opening portions constituting the grooves 40, in other words thegroove side walls 12 a in the first electrode layer 12 constituting thegrooves 40, are sloping surfaces. By this means, the cross-sectionalshape of the grooves 40 is a U-shape, corner portions of the openingthereof being chamfered (in other words, a rectangle the corner portionsof the opening of which are chamfered). The angle of the distal endcutting edge of the dicing blade 21 which has a V-shape, used to formthe chamfered sections of the grooves 40, is at least equal to 40° andat most equal to 120°.

FIG. 6 shows by way of example a schematic plan view of semiconductorelements 10 in which grooves 30 having a V-shaped cross-sectional shapeas illustrated in FIG. 4 have been formed. FIG. 6A illustrates asemiconductor element 10 provided with grooves 30 formed by means of thedicing method in FIG. 1, and FIG. 6B illustrates a semiconductor element10 provided with grooves 30 formed by means of the dicing method in FIG.2. In the case in FIG. 6A, which corresponds to the dicing method inFIG. 1, multiple grooves 30 formed in the semiconductor element 10 areformed in one direction only, and therefore the first electrode layer 12is pixelated in the shape of strips, multiple pixel electrodes arrangedin the shape of scanning lines being formed in the semiconductor element10. In the case in FIG. 6B, which corresponds to the dicing method inFIG. 2, multiple grooves 30 formed in the semiconductor element 10 forma lattice in two orthogonal directions, and therefore the firstelectrode layer 12 is pixelated in the shape of a matrix, multiple pixelelectrodes arranged in the shape of dots being formed in thesemiconductor element 10.

With regard to the dark current in a semiconductor element for detectingradiation in which V-shaped grooves 30 such as those illustrated in FIG.4 have been formed, FIG. 7 shows a graph of the results of a comparisonwith the dark current in a semiconductor element for detecting radiationin which rectangular grooves (without chamfering) such as thoseillustrated in Japanese Patent Kokai 2004-128238 have been formed. Forthe V-shaped grooves 30 and for the rectangular grooves respectively,the voltage (V) applied to multiple semiconductor elements was variedbetween 500V and 1000V, and the dark current value (nA) was measured anda mean value was obtained. It can be seen that for each applied voltage,the dark current was lower with the semiconductor elements in whichV-shaped grooves 30 had been formed. Further, the results show that thedifference increases as the applied voltage increases.

In the case of the rectangular grooves used in the comparison, thegroove side walls are cut perpendicularly from the electrode layer tothe interior of the substrate, and the side walls in the electrode layerat both sides of the groove face each other. On the other hand, in thecase of the V-shaped grooves 30, the groove side walls in the electrodelayer section are sloping surfaces (oblique surfaces), and the sidewalls in the electrode layer at both sides of the groove do not faceeach other. Further, because they are sloping surfaces, the width w ofthe openings of the grooves (see FIG. 4 and FIG. 5), in other words thewidth w of the divisions in the first electrode layer 12, is relativelywide. These are thought to be some of the factors which give rise to thedifferences shown in FIG. 7.

According to the present invention described using the abovementionedembodiments by way of example, a semiconductor element having a groovedconstruction in which the dark current is smaller than in existingexamples, and a method of forming such grooves, are provided. Therefore,in particular in semiconductor elements for detecting radiation, thedark current can be suppressed more than at present, and a semiconductorelement having improved performance can be manufactured with a goodyield. Further, according to the method of forming grooves according toat least one embodiment of the present invention, the method can beimplemented by exchanging the dicing blade for one having a suitableblade distal end portion shape, and the method therefore has theadvantage that existing equipment can be used.

Several embodiments have been described hereinabove in relation to thepresent invention. However various embodiments other than those in saidembodiments can be arrived at, and thus the present invention should beinterpreted on the basis of the scope of the patent claims.

The patent claims filed with the application are formulation proposalswithout prejudice for obtaining more extensive patent protection. Theapplicant reserves the right to claim even further combinations offeatures previously disclosed only in the description and/or drawings.

The example embodiment or each example embodiment should not beunderstood as a restriction of the invention. Rather, numerousvariations and modifications are possible in the context of the presentdisclosure, in particular those variants and combinations which can beinferred by the person skilled in the art with regard to achieving theobject for example by combination or modification of individual featuresor elements or method steps that are described in connection with thegeneral or specific part of the description and are contained in theclaims and/or the drawings, and, by way of combinable features, lead toa new subject matter or to new method steps or sequences of methodsteps, including insofar as they concern production, testing andoperating methods.

References back that are used in dependent claims indicate the furtherembodiment of the subject matter of the main claim by way of thefeatures of the respective dependent claim; they should not beunderstood as dispensing with obtaining independent protection of thesubject matter for the combinations of features in the referred-backdependent claims. Furthermore, with regard to interpreting the claims,where a feature is concretized in more specific detail in a subordinateclaim, it should be assumed that such a restriction is not present inthe respective preceding claims.

Since the subject matter of the dependent claims in relation to theprior art on the priority date may form separate and independentinventions, the applicant reserves the right to make them the subjectmatter of independent claims or divisional declarations. They mayfurthermore also contain independent inventions which have aconfiguration that is independent of the subject matters of thepreceding dependent claims.

Further, elements and/or features of different example embodiments maybe combined with each other and/or substituted for each other within thescope of this disclosure and appended claims.

Still further, any one of the above-described and other example featuresof the present invention may be embodied in the form of an apparatus,method, system, computer program, tangible computer readable medium andtangible computer program product. For example, of the aforementionedmethods may be embodied in the form of a system or device, including,but not limited to, any of the structure for performing the methodologyillustrated in the drawings.

Although the invention has been illustrated and described in detail onthe basis of the preferred example embodiment, the invention is notlimited by the disclosed examples and other variations can be derivedherefrom by the person skilled in the art, without departing from thescope of protection of the invention.

1. A semiconductor element, comprising: a substrate; and an electrodelayer formed on a surface of the substrate, the electrode layerincluding grooves to electrically divide the electrode layer, side wallsof the grooves in the electrode layer including sloping surfaces.
 2. Thesemiconductor element of claim 1, wherein a cross-sectional shape of thegrooves is a V-shape.
 3. The semiconductor element of claim 1, whereinthe cross-sectional shape of the grooves is a U-shape, corner portionsof an opening of the U-shape being chamfered.
 4. The semiconductorelement of claim 1, wherein multiple pixel electrodes are formed byelectrically dividing the electrode layer by way of the grooves, andwherein the semiconductor element is usable in the detection ofradiation.
 5. The semiconductor element of claim 4, wherein thesubstrate comprises a CdTe-based compound semiconductor.
 6. A method offorming grooves in a semiconductor element, comprising: using a dicingblade, including a blade distal end portion sharpened into a V-shape, tocut a semiconductor wafer in which multiple patterns of semiconductorelements comprising an electrode layer on a surface of a substrate areformed; and forming V-shaped grooves to divide the electrode layer ofthe semiconductor element.
 7. A method of forming grooves in asemiconductor element, comprising: using a first dicing blade, includinga blade distal end portion sharpened into a V-shape, to cut asemiconductor wafer in which multiple patterns of semiconductor elementscomprising an electrode layer on a surface of a substrate are formed;and after the cutting has been performed, using a second dicing blade,including a blade width relatively narrower than a blade width of thefirst dicing blade, to increase a depth of the V-shaped grooves, and toform grooves corner portions of openings of the V-shaped grooves whichare chamfered.
 8. A method of forming grooves in a semiconductorelement, comprising: using a first dicing blade to cut a semiconductorwafer in which multiple patterns of semiconductor elements comprising anelectrode layer on the surface of a substrate are formed; and after thecutting has been performed, using a second dicing blade, including ablade width relatively wider than a blade width of the first dicingblade and including a blade distal end portion sharpened into a V-shape,to cut corner portions of openings of the V-shaped grooves to formgrooves, corner portions of the openings of which are chamfered andwhich divide the electrode layer in each of the semiconductor elements.9. The method of claim 6, wherein multiple pixel electrodes fordetecting radiation are formed by dividing the electrode layer by way ofthe grooves.
 10. The method of claim 9, wherein the semiconductor waferis a CdTe-based compound semiconductor wafer.
 11. The semiconductorelement of claim 1, wherein the substrate comprises a CdTe-basedcompound semiconductor.
 12. The semiconductor element of claim 2,wherein the substrate comprises a CdTe-based compound semiconductor. 13.The semiconductor element of claim 3, wherein the substrate comprises aCdTe-based compound semiconductor.
 14. The method of claim 7, whereinmultiple pixel electrodes for detecting radiation are formed by dividingthe electrode layer by way of the grooves.
 15. The method of claim 14,wherein the semiconductor wafer is a CdTe-based compound semiconductorwafer.
 16. The method of claim 8, wherein multiple pixel electrodes fordetecting radiation are formed by dividing the electrode layer by way ofthe grooves.
 17. The method of claim 16, wherein the semiconductor waferis a CdTe-based compound semiconductor wafer.